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2.35 v to 5.25 v, 1 msps, 12-/10-/8-bit adcs in 6-lead sc70 ad7476a/ad7477a/ad7478a rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2011 analog devices, inc. all rights reserved. features fast throughput rate: 1 msps specified for v dd of 2.35 v to 5.25 v low power 3.6 mw at 1 msps with 3 v supplies 12.5 mw at 1 msps with 5 v supplies wide input bandwidth 71 db snr at 100 khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface spi?/qspi?/microwire?/dsp compatible standby mode: 1 a maximum 6-lead sc70 package 8-lead msop package qualified for automotive applications applications battery-powered systems personal digital assistants medical instruments mobile communications instrumentation and control systems data acquisition systems high speed modems optical sensors functional block diagram 12-/10-/8-bit successive- approximation adc control logic ad7476a/ad7477a/ad7478a gnd v dd v in sclk sdata cs t/h 02930-001 figure 1. general description the ad7476a/ad7477a/ad7478a are 12-bit, 10-bit, and 8-bit high speed, low power, successive-approximation analog-to- digital converters (adcs), respectively. the parts operate from a single 2.35 v to 5.25 v power supply and feature throughput rates up to 1 msps. the parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 13 mhz. the conversion process and data acquisition are controlled using cs and the serial clock, allowing the devices to interface with microprocessors or dsps. the input signal is sampled on the falling edge of cs , and the conversion is also initiated at this point. there are no pipeline delays associated with the parts. the ad7476a/ad7477a/ ad7478a use advanced design techniques to achieve low power dissipation at high throughput rates. the reference for the part is taken internally from v dd to allow the widest dynamic input range to the adc. thus, the analog input range for the part is 0 v to v dd . the conversion rate is determined by the sclk. product highlights 1. first 12-/10-/8-bit adcs in a sc70 package. 2. high throughput with low power consumption. 3. flexible power/serial clock speed management. the conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. this allows the average power consumption to be reduced when a power-down mode is used while not converting. the parts also feature a power-down mode to maximize power efficiency at lower throughput rates. current consumption is 1 a maximum and 50 na typically when in power-down mode. 4. reference derived from the power supply. 5. no pipeline delay. the parts feature a standard successive approximation adc with accurate control of the sampling instant via a cs input and once-off conversion control.
ad7476a/ad7477a/ad7478a rev. f | page 2 of 28 t able of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ad7476a specifications .............................................................. 3 ad7477a specifications .............................................................. 5 ad7478a specifications .............................................................. 6 timing specifications .................................................................. 8 absolute maxi mum ratings .......................................................... 10 esd caution ................................................................................ 10 pin configurations and function descriptions ......................... 11 typical performance characteristics ........................................... 12 terminology .................................................................................... 14 theory of operation ...................................................................... 15 circuit information .................................................................... 15 the converter operation .......................................................... 15 adc transfer function ............................................................. 15 typical connection diagram ....................................................... 16 analog input ............................................................................... 16 digital inputs .............................................................................. 17 modes of operation ....................................................................... 18 normal mode .............................................................................. 18 power - down mode .................................................................... 18 power - up time .......................................................................... 18 power vs. throughput rate ........................................................... 20 serial interface ................................................................................ 21 ad7478a in a 12 sclk cycle serial interface ....................... 22 microprocessor interfacing ........................................................... 23 ad7476a/ad7477a/ad7 478a to tms320c541 interface 23 ad7476a/ad7477a/ad7478a to adsp - 218x interface .... 23 ad7476a/ad7477a/ad7478a to dsp563xx interface ...... 24 application hints ........................................................................... 25 grounding and layout .............................................................. 25 evaluating the a d7476a/ad7477a performance ............... 25 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 26 automotive products ................................................................. 27 revision history 1/ 11 rev. e to rev. f changes to features section ............................................................ 1 changes to ordering guide .......................................................... 26 added automotive products section .......................................... 27 2/0 9 rev. d to rev. e changes to features .......................................................................... 1 changes to or dering guide .......................................................... 26 4/0 6 rev. c to rev. d updated format .................................................................. universal changes to ordering guide .......................................................... 2 6
ad7476a/ad7477a/ad7478a rev. f | page 3 of 28 specifications ad7476a specificatio ns v dd = 2.35 v to 5.25 v, f sclk = 20 mhz, f sample = 1 msps, t a = t min to t max , unless otherwise noted. 1 table 1. parameter a grade 2 b grade 2 y grade 2 unit test conditions/comments dynamic performance f in = 100 khz sine w ave signal -to - noise + dist ortion (sinad ) 3 70 70 70 db min v dd = 2.35 v to 3.6 v, t a = 25 c 69 69 69 db min v dd = 2.4 v to 3.6 v 71.5 71.5 71.5 db typ v dd = 2.35 v to 3.6 v 69 69 69 db min v dd = 4.75 v to 5.25 v, t a = 25 c 68 68 68 db min v dd = 4.75 v to 5.25 v signal -to - noise ratio (snr) 3 71 71 71 db min v dd = 2.35 v to 3.6 v, t a = 25 c 70 70 70 db min v dd = 2.4 v to 3.6 v 70 70 70 db min v dd = 4.75 v to 5.25 v, t a = 25 c 69 69 69 db min v dd = 4.75 v to 5.25 v total harmonic distortion (thd) 3 C80 C80 C80 db typ peak harmonic or spurious noise (sfdr) 3 C82 C82 C82 db typ inte rmodulation distortion (imd) 3 second - order terms C84 C84 C84 db typ fa = 100.73 khz, fb = 90.72 khz third - order terms C84 C84 C84 db typ fa = 100.73 khz, fb = 90.72 khz aperture delay 10 10 10 ns typ aperture jitter 30 30 30 ps typ full power bandwidth 13.5 13.5 13.5 mhz typ @ 3 db 2 2 2 mhz typ @ 0.1 db dc accuracy b and y g rades 4 resolution 12 12 12 bits integral nonlinearity 3 1.5 1.5 lsb max 0.75 lsb typ differential nonlinearity C 0.9/+1.5 C 0.9/+1.5 lsb max guaranteed no missed c odes to 12 b its 0.75 lsb typ offset error 3 , 5 1.5 1.5 lsb max 1.5 0.2 0.2 lsb typ gain error 3 , 5 1.5 1.5 lsb max 1.5 0.5 0.5 lsb typ total unadjusted error (tue) 3 , 5 2 2 lsb max analog input input voltage range 0 to v dd 0 to v dd 0 to v dd v dc leakage current 0.5 0.5 0.5 a max input capacitance 20 20 20 pf typ track - and - hold in t rack; 6 pf typ when in hold logic inputs input high voltage, v inh 2.4 2.4 2.4 v min 1.8 1.8 1.8 v min v dd = 2.35 v input low voltage, v inl 0.8 0.8 0.8 v max v dd = 5 v 0.4 0.4 0.4 v m ax v dd = 3 v input current, i in , sclk pin 0.5 0.5 0.5 a max typically 10 na, v in = 0 v or v dd input current, i in , cs pin 10 10 10 na typ input capacitance, c in 6 5 5 5 pf max
ad7476a/ad7477a/ad7478a rev. f | page 4 of 28 parameter a grade 2 b grade 2 y grade 2 unit test conditions/comments logic outputs output high voltage, v oh v dd C 0.2 v dd C 0.2 v dd C 0.2 v min i source = 200 a; v dd = 2.35 v to 5.25 v output low voltage, v ol 0.4 0.4 0.4 v max i sink = 200 a floating - state leakage current 1 1 1 a max floating - state output capacitance 6 5 5 5 pf max output coding straight (natural) binary conversion rate conversion time 800 800 800 ns max 16 sclk c ycles track - and - hold acquisition time 3 250 250 250 ns max throughput rate 1 1 1 msps max see serial interface s ection power requirements v dd 2.35/5.25 2.35/5.25 2.35/5.25 v min/max i dd digital i/ps = 0 v or v dd normal mode (static) 2.5 2.5 2.5 ma typ v dd = 4.75 v to 5.25 v, sclk on or off 1.2 1.2 1.2 ma typ v dd = 2.35 v to 3.6 v, sclk on or off normal mode (operational) 3.5 3.5 3.5 ma max v dd = 4.75 v to 5.25 v, f sample = 1 msps 1.7 1.7 1.7 ma max v dd = 2.35 v to 3.6 v, f sample = 1 msps full power - down mode (static) 1 1 1 a max typically 50 na full power - down mode (dynamic) 0.6 0.6 0.6 ma typ v dd = 5 v, f sample = 100 ksps power dissipation 7 0.3 0.3 0.3 ma typ v dd = 3 v, f sample = 100 ksps normal mode (operational) 17.5 17.5 17.5 mw max v dd = 5 v, f samp le = 1 msps 5.1 5.1 5.1 mw max v dd = 3 v, f sample = 1 msps full power - down mode 5 5 5 w max v dd = 5 v 3 3 3 w max v dd = 3 v 1 temperature ranges are as follows: a, b g rades from C 40 c to +85 c, y g rade from C 40 c to +125 c. 2 operational from v dd = 2.0 v, with input low voltage (v inl ) 0.35 v maximu m. 3 see the terminology section. 4 b and y grades, maximum specifications apply as typical figures when v dd = 4.75 v to 5.25 v. 5 sc70 values guaranteed by characterization. 6 guaranteed by characterization. 7 see the power vs. throughput rate section.
ad7476a/ad7477a/ad7478a rev. f | page 5 of 28 ad7477a specificatio ns v dd = 2.35 v to 5.25 v, f sclk = 20 mhz, f sample = 1 msps , t a = t min to t max , un les s otherwise noted. 1 table 2. parameter a grade 2 unit test conditions/comments dynamic performance f in = 100 khz sine w ave signal -to - noise + distortion (sinad) 3 61 db min total harmonic distortion (thd) 3 C72 db max peak harmonic or spurious noise (sfdr) 3 C73 db max intermodulation distortion (imd) 3 second - orde r terms C82 db typ fa = 100.73 khz, fb = 90.7 khz third - order terms C82 db typ fa = 100.73 khz, fb = 90.7 khz aperture delay 10 ns typ aperture jitter 30 ps typ full power bandwidth 13.5 mhz typ @ 3 db 2 mhz typ @ 0.1 db dc ac curacy resolution 10 b its integral nonlinearity 0.5 lsb max differential nonlinearity 0.5 lsb max guaranteed no missed c od es to 10 b its offset error 3 , 4 1 lsb max gain error 3 , 4 1 lsb max total unadjusted error (tue) 3 , 4 1.2 lsb max analog input input voltage range 0 to v dd v dc leakage current 0.5 a max input capacitance 20 pf typ track - and - hold in t rack; 6 pf typ when in hold logic inputs input high voltage, v inh 2.4 v min 1.8 v min v dd = 2.35 v input low voltage, v inl 0.8 v max v dd = 5 v 0.4 v max v dd = 3 v input current, i in , sclk pin 0.5 a max typically 10 na, v in = 0 v or v dd input current, i in , cs pin 10 na typ input capacitance, c in 5 5 pf max lo gic outputs output high voltage v oh v dd C 0.2 v min i source = 200 a, v dd = 2.35 v to 5.25 v output low voltage, v ol 0.4 v max i sink = 200 a floating - state leakage current 1 a max floating - state output capacitance 5 5 pf max output coding straight (natural) binary conversion rate conversion time 700 ns max 14 sclk c ycles with sclk at 20 mhz track - and - hold acquisition time 3 250 ns max throughput rate 1 msps max
ad7476a/ad7477a/ad7478a rev. f | page 6 of 28 parameter a grade 2 unit test conditions/comments power requirements v dd 2.35/5.25 v min/max i dd digital i/ps = 0 v or v dd normal mode (static) 2.5 ma typ v dd = 4.75 v to 5.25 v, sclk on or off 1.2 ma typ v dd = 2.35 v to 3.6 v, sclk on or off normal mode (operational) 3.5 ma max v dd = 4.75 v to 5.25 v, f sample = 1 msps 1.7 ma max v dd = 2.35 v to 3.6 v, f sample = 1 msps full power - down mode (static) 1 a max typically 50 na full power - down mode (dynamic) 0.6 ma typ v dd = 5 v, f sample = 100 ksps power dissipation 6 0.3 ma typ v dd = 3 v, f sample = 100 ksps normal mode (operational) 17.5 mw max v dd = 5 v, f sample = 1 msps 5.1 mw max v dd = 3 v, f sample = 1 msps full power - down mode 5 w max v dd = 5 v 1 temperature range is from C 40 c to +85 c. 2 operational from v dd = 2.0 v, with input high voltage (v inh ) 1.8 v min imum . 3 see the terminology section. 4 sc70 values guaranteed by characterization. 5 guaranteed by characterization. 6 see the power vs. throughput rate section. ad7478a specifica tions v dd = 2.35 v to 5.25 v, f sclk = 20 mhz, f sample = 1 msps, t a = t min to t max , unless otherwise noted. 1 table 3. parameter a grade 2 unit test conditions/comments dynamic performance f in = 100 khz s ine w ave signal -to -no ise + distortion (sinad) 3 49 db min total harmonic distortion (thd) 3 C65 db max peak harmonic or spurious noise (sfdr) 3 C65 db max intermodulatio n distortion (imd) 3 second - order terms C76 db typ fa = 100.73 khz, fb = 90.7 khz third - order terms C76 db typ fa = 100.73 khz, fb = 90.7 khz aperture delay 10 ns typ aperture jitter 30 p s typ full power bandwidth 13.5 mhz typ @ 3 db 2 mhz typ @ 0.1 db dc accuracy resolution 8 bits integral nonlinearity 3 0.3 lsb max differential nonlinearity 3 0.3 lsb max guaranteed no missed codes to eight b its offset error 3 , 4 0.3 lsb max gain error 3 , 4 0.3 lsb max total unadjusted error (tue) 3 , 4 0.5 lsb max analog input input voltage range 0 to v dd v dc leakage cur rent 0.5 a max input capacitance 20 pf typ track - and - hold in t rack; 6 pf typ when in hold
ad7476a/ad7477a/ad7478a rev. f | page 7 of 28 parameter a grade 2 unit test conditions/comments logic inputs input high voltage, v inh 2.4 v min 1.8 v min v dd = 2.35 v input low voltage, v inl 0.8 v max v dd = 5 v 0.4 v max v dd = 3 v input current, i in , sclk pin 0.5 a max typically 10 na, v in = 0 v or v dd input current, i in , cs pin 10 na typ input capacitance, c in 5 5 pf max logic outputs output high voltage, v oh v dd C 0.2 v min i source = 200 a, v dd = 2.35 v to 5.25 v output low voltage, v ol 0.4 v max i sink = 200 a floating - state leakage current 1 a max floating - state output capacitance 5 5 pf max output coding straight (natural) binary conversion rate conversion time 600 ns max 12 sclk c ycles with sclk at 20 mhz track - and - hold acquisition time 3 225 ns max throughput rate 1.2 msps max power requirements v dd 2.35/5 .25 v min/max i dd digital i/ps = 0 v or v dd normal mode (static) 2.5 ma typ v dd = 4.75 v to 5.25 v, sclk on or off 1.2 ma typ v dd = 2.35 v to 3.6 v, sclk on or off normal mode (operational) 3.5 ma max v dd = 4.75 v to 5.25 v 1.7 ma max v dd = 2.35 v to 3.6 v full power - down mode (static) 1 a max typically 50 na full power - down mode (dynamic) 0.6 ma typ v dd = 5 v, f sample = 100 ksps power dissipation 6 0.3 ma typ v dd = 3 v, f sample = 100 ksps normal mode (operational) 17.5 mw max v dd = 5 v 5.1 mw max v dd = 3 v full power - down mode 5 w max v dd = 5 v 1 temperature range is from C 40 c to +85 c. 2 operational from v dd = 2.0 v, with input high voltage (v inh ) 1.8 v min imum . 3 see the terminology section. 4 sc70 values guaranteed by characterization. 5 guaranteed by characterization. 6 see the power vs. throughput rate section.
ad7476a/ad7477a/ad7478a rev. f | page 8 of 28 timing specifications v dd = 2.35 v to 5.25 v; t a = t min to t max , unless otherwise noted. 1 table 4. parameter limit at t min , t max unit description f sclk 2 10 khz min 3 a, b g rades 20 khz min 3 y g rade 20 mhz max t convert 16 t sclk ad7476a 14 t sclk ad7477a 12 t sclk ad7478a t quiet 50 ns min minimum quie t time required between bus r elinquish and start of next c onversion t 1 10 ns min minimum cs pulse w idth t 2 10 ns min cs to sclk setup t ime t 3 4 22 ns max delay from cs until sdata thre e -s tate d isabled t 4 4 40 ns max data access t ime after sclk falling e dge t 5 0.4 t sclk ns min sclk low pulse w idth t 6 0.4 t sclk ns min sclk high p ulse w idth t 7 5 sclk to data valid hold t ime 10 ns min v dd 3.3 v 9.5 ns min 3.3 v < v dd 3.6 v 7 ns min v dd > 3.6 v t 8 6 36 ns max sclk falling edge to sdata h igh i mpedance t 7 values also apply to t 8 minimum values ns min sclk falling edge to sdata high i mpedance t power - up 7 1 s max power - up time from full p ower - d own 1 guaranteed by characterization. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. 2 mark/space ratio for the sclk input is 40/60 to 60/40. 3 minimum f sclk at which specifications are guaranteed. 4 m easured with the load circuit shown in figure 2 , and d efined as the time required for the output to cross 0.8 v or 1.8 v when v dd = 2.35 v , and 0.8 v or 2.0 v for v dd > 2.35 v. 5 measured with a 50 pf load capacitor. 6 t 8 is derived from the measured time taken b y the data outputs to change 0.5 v when loaded with the circuit shown in figure 2 . the measured number is then extrap o lated back to remove the effects of charging or discharging the 50 pf capacitor. therefore, the time, t 8 , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7 see the power - up time section .
ad7476a/ad7477a/ad7478a rev. f | page 9 of 28 timing diagrams t o output pin c l 50pf 200 a i oh 200 a i ol 1.6v 02930-002 figure 2 . load circuit for digital output timing specifications timing example 1 having f sclk 2 h tt f 1 ss, t f t 2 125 1 f sclk t acq 1 t 2 1 , t acq t 365 t 365 tf t t f 25 f t acq 4 , t acq f 25 1 f sclk t 8 t quiet t 8 36 t f 24 f t quiet , tf t t f 5 timing example 2 having f sclk 5 h tt 315 ss t f t 2 125 1 f sclk t acq 314 t 2 1 , t t acq t 664 t 664 tf t t f 25 f t acq 4 , t acq f 25 1 f sclk t 8 t quiet , t 8 36 t f 128 f t quiet , tf t t f 5 i t t t , , t f t t, t t t t 5 t quiet t i e 2, t f t t t c 4 c s sclk sdata t 2 t 6 t 3 t 4 t 7 t 5 t 8 t convert t quiet zero zero zero db11 db10 db2 db1 db0 b three-state three- state z 4 leading zeros 1 3 13 14 15 16 t 1 4 5 2 02930-003 figure 3 . ad7476a serial interface timing diagram c s sclk t 2 t convert b 1 2 5 13 14 15 16 c t 8 t quiet t a c q 12.5(1/f sclk ) 1/throughput 3 4 02930-004 figure 4 . serial interface timing example
ad7476a/ad7477a/ad7478a rev. f | page 10 of 28 absolute maximum rat ings t a = 25 c, unless otherwise noted. 1 table 5. parameter ratings v dd to gnd C 0.3 v to +7 v analog input voltage to gnd C 0.3 v to v dd + 0.3 v digital input voltage to gnd C 0.3 v to +7 v digital output voltage to gnd C 0.3 v to v dd + 0.3 v input current to any pin e xcept supplies 10 ma operating temperature range commercial (a and b grades) C40 c to +85 c industrial (y grade) C40 c to +125 c storage temperature range C65 c to +150 c junction temperature 150 c msop pa ckage ja thermal impedance 205.9 c/w jc thermal impedance 43.74 c/w sc70 package ja thermal impedance 340.2 c/w jc thermal impedance 228.9c /w lead temperature, soldering reflow (10 sec to 30 sec) 235 (0/+5) c pb -f ree temperature solder ing reflow 255 (0/+5) c esd 3.5 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those in dicated in the operational se c tion of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 transient currents of up to 100 ma do not cause scr latch - up. esd caution esd (el ectrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent dam age may occur on devices subjected to high energy electr o static discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad7476a/ad7477a/ad7478a rev. f | page 11 of 28 pin configuration s and function descrip tions top view (not to scale) 6 5 4 1 2 3 v dd gnd v in c s sdata sclk ad7476a / ad7477a / ad7478a 02930-005 figure 5 . 6 - lead sc70 pin configuration 8 7 6 5 1 2 3 4 nc = no connect v dd sd a t a v in gnd sclk nc nc top view (not to scale) ad7476a / ad7477a / ad7478a c s 02930-006 figure 6 . 8 - lead msop pin configuration table 6 . pin function descriptions mnemonic description cs chip select. active low logic in put. this input provides the dual function of initiating conversions on the ad7476a/ad7477a/ad7478a and also frames the serial data transfer. v dd power supply input. the v dd range for ad7476a/ad7477a/ad7478a is from 2.35 v to 5.25 v. gnd analog ground . ground reference point for all circuitry on ad7476a/ad7477a/ad7478a. refer a ll analog input signals to this gnd voltage. v in analog input. single - ended analog input channel. the input range is 0 v to v dd . sdata data out. logic output. the conversio n result from ad7476a/ad7477a/ad7478a is provided on this output as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream from the ad7476a consists of fou r leading zeros followed by 1 2 bits of conversion data t hat are provided msb first. the data stream from the ad7477a consists of fou r leading zeros followed by 10 bits of conversion data followed by two trailing zeros, provided msb first. the data stream from the ad7478a consists of fo ur leading zeros followe d by 8 bits of conversion data follow ed by four trailing zeros that are provided msb first. sclk serial clock. logic input. sclk provides the serial clock for accessing data from the part. this clock input is also used as the clock source fo r the conver sion process of ad7476a/ad7477a/ad7478a . nc no connect.
ad7476a/ad7477a/ad7478a rev. f | page 12 of 28 typical performance characteristics figure 7 , figure 8 , and figure 9 each show a typical fft plot for the ad7476a, ad7477a, and ad7478a, respectively, at a 1 msps sa m ple rate and 100 khz input frequency. figure 10 shows the signal - to - (noise + distortion) ratio performance vs. the input frequency for various supply voltages while sa m pling at 1 msps with an sclk frequency of 20 mhz for the ad747 6a. figure 11 and figure 12 show inl and dnl performance for the ad7476a . figure 13 shows a graph of the total harmonic distortion v s. the analog input frequency for different source impedances when using a supply voltage of 3.6 v and sampling at a rate of 1 msps (see t he analog input section). figure 14 shows a graph of the total harmonic distortion vs. the an a log input signal frequency for various supply voltages while sa m pling at 1 msp s with an sclk frequency of 20 mhz. freq uency (khz) 5 ?55 ?115 0 500 50 snr (db) 100 150 200 250 300 350 400 450 ?15 ?35 ?75 ?95 8192 point fft v dd = 2.7v f sample = 1msps f in = 100khz sinad = 72.05db thd = ?82.87db sfdr = ?87.24db 02930-007 figure 7 . ad7476a dynamic performance at 1 msps freq uency (khz) ?45 ?105 snr (db) ?5 ?25 ?65 ?85 8192 point fft v dd = 2.35v f sample = 1msps f in = 100khz sinad = 61.67db thd = ?79.59db sfdr = ?82.93db 0 500 50 100 150 200 250 300 350 400 450 02930-008 figure 8 . ad7477a dynamic performance at 1 msps freq uency (khz) 5 ?25 ?55 snr (db) ?5 ?15 ?35 ?45 8192 point fft v dd = 2.35v f sample = 1msps f in = 100khz sinad = 49.77db thd = ?75.51db sfdr = ?70.71db 0 500 50 100 150 200 250 300 350 400 450 ?75 ?65 ?85 ?95 02930-009 figure 9 . ad7478a dynamic performanc e at 1 msps freq uency (khz) ?66 ?69 ?72 10 1000 sinad (db) 100 ?67 ?68 ?70 ?71 ?73 ?74 v dd = 5.25v v dd = 2.35v v dd = 2.7v v dd = 4.75v v dd = 3.6v 02930-010 figure 10 . ad7476a sinad vs. input frequency at 1 msps
ad7476a/ad7477a/ad7478a rev. f | page 13 of 28 code 1.0 0.4 ?0.2 0 1024 inl err or (lsb) 512 0.8 0.6 0.2 0 ?0.4 ?0.6 ?0.8 ?1.0 1536 2048 2560 3072 3584 4096 v dd = 2.35v temp = 25c f sample = 1msps 02930-011 figure 11 . ad7476a inl performance code 1.0 0.4 ?0.2 0 1024 dnl err or (lsb) 512 0.8 0.6 0.2 0 ?0.4 ?0.6 ?0.8 ?1.0 1536 2048 2560 3072 3584 4096 v dd = 2.35v temp = 25 c f sample = 1msps 02930-012 figure 12 . ad7476a dnl performance input freq uency (khz) 0 ?30 ?60 10 1000 thd (db) 100 ?10 ?20 ?40 ?50 ?70 ?80 ?90 v dd = 3.6v r in = 10k? r in = 1k? r in = 130? r in = 13? r in = 0? 02930-013 figure 13 . thd vs. analog input frequency for various source impedance s input freq uency (khz) ? 60 ?75 ?90 10 1000 thd (db) 100 ?65 ?70 ?80 ?85 v dd = 5.25v v dd = 2.35v v dd = 2.7v v dd = 4.75v v dd = 3.6v 02930-014 figure 14 . thd vs. analog input frequency for various supply voltages
ad7476a/ad7477a/ad7478a rev. f | page 14 of 28 terminology integral nonlinearity (inl) inl is the maximum deviation from a straigh t line passing through the endpoints of the adc transfer function. for the ad7476a/ad7477a/ad7478a, the endpoints of the transfer function are zero scale ( 1 lsb below the first code transition ) , and full scale ( 1 lsb above the last code transition ) . differ ential nonlinearity (dnl) dnl is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, agnd + 1 lsb. gain error this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal, that is, v ref C 1 lsb after the offset error has been adjusted out. track - and- hold acquisition time the track - and - hold amplif ier returns to track mode at the end of a conversion. the track - and - hold acquisition time is the time required for the output of the track - and - hold amplifier to reach its final value, within ? 0.5 lsb, after the end of conversion. see the serial interface section for more details. signal -to - (noise + distortion) ratio (sinad) this is the measured ratio of signal - to - (noise + distortion) at the output of t he adc . the signal is the rms ampl i tude of the fundamental. noise is the sum of all nonfundame n tal signals up to half the sampling frequency ( f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitiza - tion process; the more levels, the smaller the quant i zation noise. the theoretical signal - to - (noise + disto r tion) ratio for an ideal n - bit converter with a sine wave i n put is given by signal - to - (noise + distortion) = (6.02 n + 1.76) db. thus, it is 74 db for a 12- bit conve rter, 62 db for a 10 - bit co n verter, and 50 db for an 8 - bit converter. total unadjusted error (tue) this is a comprehensive specification that includes the gain, linearity, and offset errors. total harmonic distortion (thd) total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. it is defined as 1 2 6 2 5 2 4 2 3 2 2 v v v v v v thd + + + + = log 20 ) db ( where v 1 is the rms amplitude of the fundamental, and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or s purious noise (sfdr) peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specificat ion is dete r mined by the largest harmonic in the spectrum. for adcs where the harmonics are buried in the noise floor, it is a noise peak . intermodulation distortion (imd) with inputs consisting of sine waves at two frequencies, fa and fb, any active devic e with nonlinearities create distortion products at sum and difference frequencies of mfa, ? nfb, where m and n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n are equal to zero. for e x ample, the second - order te rms include (fa + fb) and (fa C fb), and the third - order terms include (2fa + fb), (2fa C fb), (fa + 2fb), and (fa C 2fb). the ad7476a/ad7477a/ad7478a are tested using the ccif standard where two input freque ncies are used (see fa and fb in the specifications section ). in this case, the second - order terms are usually distanced in frequency from the original sine waves, while the third - order terms are usually at a frequency close to the input frequencies. as a resul t, the second - and third - order terms are specified separately. the calculation of the inte r modulation distortion is per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in d ecibel s.
ad7476a/ad7477a/ad7478a rev. f | page 15 of 28 theory of operation c ircuit information the ad7476a/ad7477a/ad7478a are fast, micropower, 12- /10 - / 8 - bit , single - supply analog - to - digital converters (adcs) , respectively. the parts can be operated from a 2.35 v to 5.2 5 v supply. when operated from either a 5 v suppl y or a 3 v supply, the ad7476a/ ad7477a/ad7478a are capable of throughput rates of 1 msps when provided with a 20 mhz clock. the ad7476a /a d7477a/ad7478a provide the user with an on - chip, track - and - hold adc an d a serial interface housed in a tiny 6 - lead sc70 or 8 - lead msop package, offering the user considerable space - saving advantages over alternative solutions. the serial clock input accesses data from the part but also pro - vides the clock source for the succ essive - approximation adc . the analog input range is 0 v to v dd . th e adc does not require an external reference or an on - chip reference. the reference for the ad7476a/ad7477a / ad7478a is derived from the power supply and , thus , gives the widest dynamic input range. the ad7476a/ad7477a/ ad7478a also feature a power - down option to allow power saving between conversions. the power - down feature is implemented across the standard serial i n terface , as described in the modes o f operation section. the converter operation ad7476a/ad7477a/ad7478a are successive approximation, analog - to - digital converter s based around a cha rge redistrib u - tion dac. figure 15 and figure 16 show simplified schematics of the adc . figure 15 shows the adc during its acquisition phase. sw2 is closed and sw1 is in position a, the comparator is held in a balanced condition, and the s ampling capacitor a c quires the signal on v in . charge redistrib ution d a c contr ol logic comp ara t or sw2 sampling cap a cit or a c q uisition phase sw1 a b a gnd v dd /2 v in 02930-015 figure 15 . adc acquis i tion phase wh en the adc starts a conversion ( see figure 16), sw2 opens and sw1 moves to position b, causing the compa rator to b e come unbalanced. the control logic and the charge redistrib u tion dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. figure 17 shows the adc transfer function. charge redistrib ution d a c contr ol logic comp ara t or sw2 sampling cap a cit or conversion phase sw1 a b a gnd v dd /2 v in 02930-016 figure 16 . adc conversion phase adc transfer function the output coding of the ad7476a/ad7477a/ad7478a is straight binary. the designed code transitions occur at the su c cessive integer lsb values, that is , 1 lsb, 2 lsb, and so on. the lsb size is v dd /4096 for the ad7476a, v dd /1024 for the ad7477a, and v dd /256 for the ad7478a. the ideal transfer characteristic for the ad7476a/ad7477a/ad7478a is shown in figure 17. 000...000 0v adc code analog input 111...111 000...001 000...010 111...110 111...000 011...111 1lsb = v dd /256 (ad7478a) 1lsb +v dd ? 1lsb 1lsb = v dd /1024 (ad7477a) 1lsb = v dd /4096 (ad7476a) 02930-017 figure 17 . ad7476a/ad7477a/ad7478a transfer characteristic
ad7476a/ad7477a/ad7478a rev. f | page 16 of 28 typical connection d iagram figure 18 shows a typical connection diagram for the a d7476a / ad7477a/ad7478a. v ref is taken internally from v dd and, as such, v dd should be well decoupled. this provides an analog input range of 0 v to v dd . the conversion result is output in a 16- bit word with four leading zeros followed by the msb of the 12- bit, 10 - bit, or 8 - bit result. the 10 - bit result from the ad7477a is followed by two trailing zeros, and the 8 - bit result from the ad7478a is followed by four trailing zeros. altern a tively, because the supply current required by the ad7476a/ad7477a/ad7478a is so low, a precision reference can be used as the supply source to t he ad7476a/ad7477a/ ad7478 a . a ref19x voltage refer - ence ( ref195 for 5 v or ref193 for 3 v) can be used to supply the required voltage to the adc (see figure 18 ). this configuration is especially useful if the power supply i s quite noisy , or if the system supply voltages are at some v alue other than 5 v or 3 v (for example, 15 v). the ref19x outputs a steady voltage to the ad7476a/ ad7477a/ad7478a . if the low dropout ref193 is used, the current it needs to su p ply to the ad74 76a/ad7477a/ ad7478a i s typically 1. 2 ma. when the adc is converting at a rate of 1 msps, the ref193 needs to supply a maximum of 1.7 ma to the ad7476a/ad7477a/ ad7478a. the load regu lation of the ref193 is typ i cally 10 ppm/ma (v s = 5 v), resulting in an error of 17 ppm (51 v) for the 1.7 ma drawn from it. this corresponds to a 0.069 lsb error for the ad7476a with v dd = 3 v from the ref193 , a 0.017 lsb error for the ad7477a, and a 0.0043 lsb error for the ad7478a. for applications where power co n sumption is a concern, use the power - down mode of the adc and the sleep mode of the ref19x reference to improve power performance. se e the modes of operation section. ad7476a / ad7477a / ad7478a sclk sd a t a c s v in gnd 0 v t o v dd input v dd c/p serial interface 0.1f 1f t ant ref193 1.2ma 680nf 10f 0.1f 3v 5v suppl y 02930-018 figure 18 . ref193 as power supply to ad7476a/ ad7477a/ad7478a table 7 provides typical performance data with various references used as a v dd source for a 100 khz input tone at room temperature under the same setup conditions. table 7 . ad7476a typical performance for various voltage references reference tied to v dd ad7476a snr performanc e (db) ad780 @ 3 v 72.65 ref193 72.35 ad780 @ 2.5 v 72.5 ref 192 72.2 ref43 72.6 analog input figure 19 shows an equivalent circuit of the analog input stru c ture of the ad7476a/ad7477a/ad7478a. the two diodes, d1 and d2, provide esd protection f or the analog input. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mv. this causes the diodes to become forward - biased and start conducting current into the substrate. the maximum current these di odes can conduct without causing irreversible da mage to the part is 10 ma. the c apacitor c1 in figure 19 is typically about 6 pf and can pr i marily be attr ibuted to pin capacitance. the r esistor r1 is a lumped compo nent made up of the on resistance of a switch. this resistor is typically about 100 ? . the c apacitor c2 is the adc sampling capacitor and has a capacitance of 20 pf typ i cally. for ac applications, removing high frequency components from the analog input signal is recommen ded by use of a band - pass filter on the relevant analog input pin. in applications where harmonic distortion and signal - to - noise ratio are critical, drive the analog input from a low impedance source. large source impedances significantly affect the ac performance of the adc , necessitating the use of an input buffer ampli fier. the choice of the op amp is a function of the particular application. d1 d2 r1 c2 20pf v dd v in c1 6pf conversion phase ? switch open track phase ? switch closed 02930-019 figure 19 . equivalent analog input circuit
ad7476a/ad7477a/ad7478a rev. f | page 17 of 28 table 8 provides typical performance data with various op amps us ed as the input buffer for a 100 khz input tone at room temperature under the same setup conditions. table 8 . ad7476a typical performance with various input buffers, v dd = 3 v op amp in the input buffer ad7476a snr performance (db) ad711 72.3 ad797 72.5 ad845 71.4 when no amplifier is used to drive the analog input, limit the source impedance to low values. the maximum source imped - ance depend s on the amount of total harmonic distortion (thd) that can be tolerated. the thd increase s as the source impedance increases , degrading the performance (s ee figure 13) . digital inputs the digital inputs applied to the ad7476a/ad7477a/ad7478a are not limited by the maximum ratings that limit the analog input. instead, the digital inputs applied can reach 7 v and are not restricted by the v dd + 0.3 v limit as on the analog input. for example, if operating the ad7476a/ad7477a/ad7478a with a v dd of 3 v, u s e 5 v logic levels o n the digital inputs. however, note that the data output on sdata still ha s 3 v logic levels when v dd = 3 v. another advantage of sclk and cs not being restricted by the v dd + 0.3 v limit is that power su p ply sequencing issues are avoided. if cs or sclk are applied b e fore v dd , there is no risk of latch - up as there would be on the analog input if a signal greater than 0.3 v were applied prior to v dd .
ad7476a/ad7477a/ad7478a rev. f | page 18 of 28 m odes of operation the mode s of operation for the ad7476a/ad7477a/ad7478a are selected by controlling the (logic) state of the cs signa l during a conversion. there are two possible modes of operation: norm al and power - down. the point at which cs is pulled high after the co nversion has been initiated determine s whet her the ad7476a/ ad7477a/ad7478a enter s power - down mode . similarly, if already in power - down , cs can control whether the device return s to normal operation or remain s in power - down. these modes of operation are designed to provide flexible power management options. these options can be chosen to optimize the power dissipation/throughput rate ratio for different a pplication requirements. normal mode this mode is intended for the fastest throughput rate perfor mance . in normal mode, the user does not have to worry about any power - up times because a d7476a/ad7477a/ad7478a remain fully powered at all times . figure 20 shows the general diagram of the operation of the ad7476a/ad7477a/ad7478a in this mode. the conversion is initiated on the falling edge of cs as described in the serial interface section. to ensure that the part remains fully powered up at all times, cs must remain low until at least 10 sclk falling edges have elapsed after the falling edge of cs . if cs is brought high any time after the 10th sclk falling edge but before the end of the t convert , the part remains powere d up, but the conversion is terminated and sdata go es back into three - state. for the ad7476a, 16 serial clock cycles are required to complete the conversion and access the complete conversion results. for the ad7477a and ad7478a, a minimum of 14 and 12 serial clock cycles are required to com - plete the conversion and access the complete conversion results, respectively. cs can idle high until the next conversion or idle low until cs returns high sometime prior to the next conversion (effectively idling cs low). once a data transfer is complete (sdata has returned to three - state), another conve rsion can be initiated after the quiet time, t quiet , has elapsed by bringing cs low again. power - down mode this mode is intended for use in applications where slower throughput rates are required; either the adc is powered down between ea ch conversion, or a series of conversions is performed at a high throughput rate and the adc is then powered down for a relatively long duration between these bursts of se v eral conversions. when the ad7476a/ad7477a/ ad7478a are in power - down, all analog cir cuitry is powered down. to enter power - down, the conversion process must be interrupted by bringing cs high anywhere after the second falling edge of sclk and before the 10th falling edge of sclk, as shown in figure 22 . once cs has been brought high in this window of sclks, the part enter s power - down, the conversion that was initiated by the falling edge of cs is terminated, and sdata goes back into three - state. if cs is brought high before the se c ond sclk falling edge, the par t remain s in normal mode and does not power down. this avoid s accidental power - down due to glitches on the cs line. in order to exit this mode of oper a ti on and power up the ad7476a/ad7477a/ad7478a again, a dummy conversion is performed. on the falling edge of cs , the device begin s to power up and continue s to power up as long as cs is held low until after the falling edg e of the 10th sclk. the device is fully powered up once 16 sclks have elapsed, and valid data result s from the next conversion , as shown in figure 24 . if cs is brought high before the 10th falling edge of sclk, then the ad7476a/ad7477a/ad7478a go back into power - down. this avoids accidental power - up due to glitches on the cs line or an inadvertent burst of eight sclk cycles while cs is low. a lthough the device ca n begin to power up on the falling edge of cs , it powers down again on the rising edge of cs as long as it occurs before the 10th sclk falling edge. power - up time the power - up time of the ad7476a/ad7477a/ad7478a is 1 s, meaning that with any frequency of sclk up to 20 mhz, one d ummy cycle is always sufficient to allow the d e vice to power up. once the dummy cycle is complete, the adc is fully powered up and the input signal is acquired properly. the quiet time, t quiet , mu st still be allowed from the point where the bus goes back into three - state after the dummy co n version to the next falling edge of cs . when running at a 1 msps throughput rate, the ad7476a/ad7477a/ad7478a power up and acquire a signa l wit hin 0.5 lsb in one dummy cycle, that is , 1 s. when powering up from the power - down mode with a dummy cycle, as in figure 22 , the track - and - hold that was in hold mode while the part was powered down returns to tra ck mode after the first sclk edge the part receives after the falling edge of cs . this is shown as point a in figure 22 . although at any sclk frequency , one dummy cycle is sufficient to power up t he device and acquire v in , it does not necessarily mean that a full dummy cycle of 16 sclks must always elapse to power up the device and acquire v in fully; 1 s is sufficient to power up the device and acquire the input signal. if, for e xample, a 5 mhz sc lk frequency i s applied to the adc, the cycle time becomes 3.2 s. in one dummy cycle, 3.2 s, the part powers up and v in a c quires fully. however, after 1 s with a 5 mhz sclk, only five sclk cycles would have elapsed. at this stage , the adc would fully po wer up and acquire the signal . in this case, the cs can be brought high after the 10th sclk falling edge and brought low again after a time, t quiet , to initiate the conversion.
ad7476a/ad7477a/ad7478a rev. f | page 19 of 28 sd a t a sclk c s 1 10 12 14 16 ad7476a/ad7477a/ad7478a 02930-020 valid data figure 20 . normal mode operatio n three-st a te sd a t a sclk c s 1 10 12 14 16 2 02930-021 figure 21 . entering power - down mode invalid data sd a t a sclk c s 1 10 12 14 16 a 1 16 valid data the p ar t is full y po wered up with v in full y a cq uired the p ar t b eg i n s t o po wer up 02930-022 figure 22 . exiting power - down mode when power supplies are first applied to the ad7476a/ad7477a/ ad7478a , th e adc can power up in either the power - down or norma l mode s . because of this, it is best to allow a dummy cycle to elapse to ensure that the part is fully powered up before a t tempting a valid conversion. likewise, if it is intended to keep the part in the power - down mode while not in use and the user wishes the part to power up in powe r - down mode, the dummy cycle can be used to ensure that the device is in power - down by executing a cycle such as that shown in figure 22 . once supplies are applied to the ad7476a/ad7477 a/ad7478a, the power - up time is the same as that when poweri ng up from the power - down mode . it takes approximately 1 s to power up fully if the part powers up in normal mode. it is not necessary to wait 1 s b e fore executing a dummy cycle to ensure the de sired mode of operation. instead, a dummy cycle can occur directly after power is supplied to the adc. if the first valid conversion is perfor med directly after the dummy conversion, care must be taken to ensure that an adequate acquisition time has been a l lowed. as mentioned earlier, whe n powering up from the power - dow n mode, the part returns to tra ck upon the first sclk edge applied after the falling edge of cs . however, when the adc initially powers up after supplies are applied, the t rack - and - hold is already in track. this means, assuming one has the facility to monitor the adc supply current, if the adc powers up in the desired mode of operation and thus a dummy cycle is not required to change the mode, a dummy cycle is not required t o place the track - and - hold into track.
ad7476a/ad7477a/ad7478a rev. f | page 20 of 28 power v s. throughput rate by using the power - down mode on the ad7476a/ad7477a/ ad7478a when not converting, the average power consump - tion of the adc decreases at lower throughput rates. figure 23 shows that as the throughput rate is reduced, the device remains in its power - down state longer and the average power consumption over time drops accordingly. for example, if the ad7476a/ad7477a/ad7478a ope r ate in a continuous sam pling mode with a throughput rate of 100 ksps and an sclk of 20 mhz (v dd = 5 v) and the devices are placed in the power - down mode between conversions, the power consu mption is calculated as follows: the power dissip a tion during normal operation is 17.5 mw (v dd = 5 v). if the power - u p time is one dummy cycle, that is , 1 s, and the r e maining conversion time is another cycle, that is, 1 s, the n the ad7476a/ad7477a/ad7478a diss i pate 17.5 mw for 2 s during each conversion cycle. if the throughput rate is 10 0 ksps, the cycle time is 10 s , then the a v erage power dissipated during each cycle is (2/10 ) (17.5 mw) = 3.5 mw . if v dd = 3 v, sclk = 20 mhz, and the devices are again in pow e r - down mode between conversions, then the power dissipation du r ing normal o peration is 5.1 mw. th us, the ad7576a/ad7477a/ad8478a dissipate 5.1 mw for 2 s during each conversion cycle. with a throughput rate of 100 ksps, the average power dissipated during each cycle is (2/ 10) (5.1 mw) = 1.02 m w. figure 23 shows the power vs. the throughput rate when using the power - down mode between conversions with both 5 v and 3 v supplies . the power - down mode is intended for use with throughput rates of approximately 333 ksps or less , because at hig her sampling rates, the power - down mode produces no power savings. throughput (ksps) 100 0.1 0 power (mw) 10 1 0.01 50 100 150 200 250 300 350 v dd = 5v , sclk = 20mhz v dd = 3v , sclk = 20mhz 02930-023 figure 23 . power vs. throughput
ad7476a/ad7477a/ad7478a rev. f | page 21 of 28 serial interface figure 24, figure 25, and figure 26 show the detailed timing diagrams for serial interfacing to the ad7476a, ad7477a, and ad7478a, respectively. the serial clock provides the conversion clock and also controls the transfer of information from the ad7476a/ad7477a/ad7478a during conversion. the cs signal initiates the data transfer and conversion process. the falling edge of cs puts the track-and-hold into hold mode and takes the bus out of three-state; the analog input is sampled at this point. also, the conversion is initiated at this point. for the ad7476a, the conversion requires 16 sclk cycles to complete. once 13 sclk falling edges have elapsed, the track- and-hold goes back into track on the next sclk rising edge, as shown in figure 24 at point b. on the 16th sclk falling edge, the sdata line goes back into three-state. if the rising edge of cs occurs before 16 sclks have elapsed, the conversion is terminated and the sdata line goes back into three-state; otherwise, sdata returns to three-state on the 16th sclk falling edge, as shown in figure 24. sixteen serial clock cycles are required to perform the conversion process and to access data from the ad7476a. for the ad7477a, the conversion requires 14 sclk cycles to complete. once 13 sclk falling edges have elapsed, the track- and-hold goes back into track on the next rising edge as shown at point b in figure 25. if the rising edge of cs occurs before 14 sclks have elapsed, the conversion is terminated and the sdata line goes back into three-state. if 16 sclks are considered in the cycle, sdata returns to three-state on the 16th sclk falling edge, as shown in figure 25. for the ad7478a, the conversion requires 12 sclk cycles to complete. the track-and-hold goes back into track on the rising edge after the 11th falling edge, as shown in figure 26 at point b. if the rising edge of cs occurs before 12 sclks have elapsed, the conversion is terminated and the sdata line goes back into three- state. if 16 sclks are considered in the cycle, sdata returns to three-state on the 16th sclk falling edge, as shown in figure 26. cs sclk s data t 2 t 6 t 3 t 4 t 7 t 5 t 8 t convert t quiet zero zero zero db11 db10 db2 db1 db0 b three-state three- state z 4 leading zeros 1 3 13 14 15 16 t 1 1/throughput 245 02930-024 figure 24. ad7476a serial interface timing diagram sclk 1 5 13 15 three-state t 4 2 16 t 5 t 3 t 2 db9 db8 db0 zero t 6 t 7 t 8 14 4 leading zeros zero zero zero z t 1 1/ throughput zero 2 trailing zeros sdata t convert t quiet b three-state cs 4 02930-025 3 figure 25. ad7477a serial interface timing diagram cs sclk 1 13 15 sdata 4 leading zeros three-state t 4 2 3 16 t 5 t 3 t 2 three-state db7 t 6 t 7 t 8 14 zero zero zero z t 1 1/ throughput zero zero zero zero 11 12 4 trailing zeros t convert t quiet b 4 02930-026 figure 26. ad7478a serial interface timing diagram
ad7476a/ad7477a/ad7478a rev. f | page 22 of 28 cs going low clocks out the first leading zero to be read in by the microcontroller or dsp. the remaining data is then clocked out by subsequent sclk falling edges beginning with the se c ond leading zero. thus, the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. for the ad7 476a, the final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. in applications with a slower sclk, it is possible to read in data on each sclk rising edge. in this case, the first f alling edge of sclk clocks out the second leading zero, which can be read in the first rising edge. however, the first leading zero that was clocked out when cs went low will be missed, unless it was not read in the first falling edge. th e 15th falling edge of sclk clock s out the last bit and it can be read in the 15th rising sclk edge. if cs goes low just after one sclk falling edge has elapsed, cs clock s out the first leading zero as it did before, and it can be read in the sclk rising edge. the next sclk falling edge clock s out the second leading zero, and it can be read in the following rising edge. ad7478a in a 12 sclk cycle serial interfa ce for the ad7478a, if cs is brought high i n the 12th rising edge after four leading zeros and eight bits of the conversion have been provided, the part can achieve a 1.2 msps throughput rate. for the ad7478a, the track - and - hold goes back into track in the 11th rising edge. in this case, a f sclk = 20 mhz and a throughput of 1.2 msps give a cycle time of t 2 + 10.5(1/ f scl k ) + t acq = 833 ns with t 2 = 10 ns min, this leaves t acq to be 298 ns. this 298 ns satisfies the requirement of 225 ns for t acq . from figure 27, t acq is comprised of 0.5 (1/ f sclk ) + t 8 + t quiet where t 8 = 36 ns maximum . this allows a value of 237 ns for t quiet , satisfying the minimum requirement of 50 ns . sclk t 1 1 5 11 sdata three-state db7 db6 db0 zero zero zero 4 leading zeros 2 3 t 2 t 8 12 1/ throughput t acq 10.5(1/ f sclk ) t convert t quiet b three-state c s 4 02930-027 z figure 27 . ad7478a in a 12 sclk cycle serial interface
ad7476a/ad7477a/ad7478a rev. f | page 23 of 28 microprocessor inter facing the serial interface on the ad7476a/ad7477a/ad7478a a l lows the part to be directly connected to a range of different microprocessors. this section explain s how to interface the ad7476a/ad7477a/ad7478a with some of the more co m mo n microcontroller and dsp serial interface protocols. ad7476a/ad7477a/ad74 78a to tms320c541 interface the serial interface on the tms320c541 uses a continuous s e rial clock and frame synchronization signals to synchronize the data transfer operations with p eripheral devices, such as the ad7476a/ad7477a/ad7478a. the cs input allows easy i n terfacing between the tms3 20c541 and the ad7476a/ ad7477a/ ad7478a without any glue logic required. the serial port of the tms320c541 is set up to operate in burst mode (fsm = 1 in the serial port control register, spc) with internal serial clock clkx (mcm = 1 in the spc register) and internal frame signal (txm = 1 in the spc register), so both pins are configured as outputs. for the ad7476a, set the word le ngth to 16 bits (fo = 0 in the spc register). this dsp only allows frames with a word length of 16 bits or 8 bits. therefore, in the case of the ad7477a and ad7478a where 14 bits and 12 bits are required, the fo bit is set up to 16 bits. this means that to obtain the conversion result, 16 sclks are needed. in both situations, the remaining sclks clock out trailing zeros. for the ad7477a, two trailing zeros are clocked out in the last two clock cycles; for the ad7478a, four trailing zeros are clocked out. to summarize, the values in the spc register are fo = 0 fsm = 1 mcm = 1 txm = 1 the format bit, fo, can be set to 1 to set the word length to eight bits in order to implement the power - down mode on the ad7476a/ad7477a/ad7478a. the connection diagram is sho wn in figure 28 . f or signal processing applications, it is imperative that the frame synchroniz a tion sig nal from the tms320c541 provide equidistant sampling. ad7476a / ad7477a / ad7478a 1 sclk sd a t a c s clkx clkr fsx fsr tms320c541 1 1 additional pins omitted for clarity. dr 02930-028 figure 28 . interfacing to th e tms320c541 ad7476a/ad7477a/ad74 78a to adsp-218x interface the adsp - 218x family of dsps are interfaced directly to the ad7476a/ad7477a/ad7478a witho ut any glue logic r e quired. set up the sport control register as follows: tfsw = rfsw = 1, a l ternate f rami ng invrfs = invtfs = 1, active l ow f rame s ignal dtype = 00, r ight justify d ata isclk = 1, internal serial c lock tfsr = rfsr = 1, f rame every w ord irfs = 0, sets up rfs as an i nput itfs = 1, sets up tfs as an o utput slen = 1111, 16 b its for the ad7476a slen = 1101, 14 b its for the ad7477a slen = 1011, 12 b its for the ad7478a
ad7476a/ad7477a/ad7478a rev. f | page 24 of 28 to implement the power - down mode, set slen to 0111 to issue an 8 - bit sclk burst. the connection diagram is shown in figure 29 . the adsp - 218x ha s the tfs and rfs of the sport tied together, with tfs set as an output and rfs set as an input. the dsp operates in alternate framing mode, and the sport control register is set up as described. the frame synchroniz a tion signal generated on the tfs is tie d to cs , and, as with all signal processing applications, equidistant sampling is nece s sar y. however, in this example, the timer interrupt is used to control the sampling rate of the adc and, under certain cond i tions, equidistant sampling may not be achieved. ad7476a / ad7477a / ad7478a 1 sclk sd a t a c s sclk dr rfs tfs adsp-218x 1 1 additional pins omitted for clarity. 02930-029 figure 29 . interfacing to the adsp - 218x t he timer registers, for example, are loaded with a value that provides an interrupt at the required sample interval. when an interrupt is received, a value is transmi tted with tfs/dt (adc control word). the tfs control s the rfs and , thus , the reading of data. the frequency of the serial clock is set in the sclkdiv register. when the instruction to transmit with tfs is given, that is , tx0 = ax0, the state of the sclk is checked. the dsp waits until the sclk has gone high, low, and high before transmission starts . if the timer and sclk values are chosen such that the instruction to transmit occurs on or near the rising edge of sclk, the data can be transmitted or it can w ait until the next clock edge. for example, the adsp - 2111 has a master clock frequency of 16 mhz. if the sclkd iv register is loaded with the v alue 3, an sclk of 2 mhz is obtained and eight master clock periods will elapse for every one sclk p e riod. if the timer registers are loaded with the v alue 803, 100.5 sclks occur between interrupts and , subsequently , between transmit in structions. this situation result s in nonequidistant sampling as the transmit instruction is occurring on an sclk edge. if the number of sclks between interrupts is a whole integer figure of n, equidistant sampling is implemented by the d s p. ad7476a/ad7477a/ad74 78a to dsp563xx inte r face the connection diagram in figure 30 shows how the ad7476 a/ad7477a/ad7478a can be connected to the ssi (synchronous serial interface) of the dsp563xx family of dsps from motorola. the ssi is operated in sync hronous and normal mode (syn 1 = and mod = 0 in control register b, crb) with internally generated word le ngth fra me sync for both tx and rx (bit fsl1 = 0 and bit f sl0 = 0 in crb). set the word length in control register a (cra) to 16 by setting bit wl2 = 0, bit wl1 = 1, and bit wl0 = 0 for the ad7476a. the word length for the ad7478a can be set to 12 bits (wl 2 = 0, wl1 = 0, and wl0 = 1). this dsp does not offer the option for a 14 - bit word length, so the ad7477a word length is set up to 16 bits, the same as the ad7476a. for the ad7477a, the conversion pro c ess uses 16 sclk cycles , with the last two clock period s cloc k ing out two trailing zeros to fill the 16 - bit word. to implement the power - down mode on the ad7476a/ad7477a/ ad7478a, the word length can be changed to eight bits by se t ting bit wl2 = 0, bit wl1 = 0, and bit wl0 = 0 in cra. the fsp bit in the crb r egister can be set to 1, meaning the frame goes low and a conversion starts. lik e wise, by means of t he bit scd2, bit sckd, and bit shfd in the crb register, it establishe s that pi n sc2 (the frame sync signal) and pin sck in the serial port are configured a s outputs and the msb is shifted first. in summary: mod = 0 syn = 1 wl2, wl1, and wl0 depend on the word length fsl1 = 0 and fsl0 = 0 fsp = 1, negative frame s ync scd2 = 1 sckd = 1 shfd = 0 note that for signal processing applications, it is imperative tha t the frame synchronizati on signal from the dsp563xx provide equidistant sampling. ad7476a / ad7477a ad7478a 1 sdata sclk c s dsp563xx 1 sck srd sc2 1 additional pins omitted for clarity. 02930-030 figure 30 . interfacing to the dsp563xx
ad7476a/ad7477a/ad7478a rev. f | page 25 of 28 application hints grounding and layout design t he printed circuit board that houses the ad7476a/ ad7477 a/ad7478a such that the analog and dig i tal sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be sep a rated easily. a minimum etch technique is generally best for ground planes because it gi ves the best shielding. join d igital and analog ground planes at only one place. if the ad7476a/ad7477a/ ad7478a is in a system where multiple devices r e quire an agnd to dgnd connection, make the co n nection at one point only, a star ground point that is es tablished as close as possible to the ad7476a/ad7477a/ad7478a. avoid running digital line s under the device as these couple noise onto the die. allow the analog ground plane to run under the ad7476a/ad7477a/ad7478a in order to avoid noise coupling. use as large a trace as possible on t he power supply lines to the ad7476a/ad7477a/ad7478a to provide low i m pedance paths and reduce the effects of glitches on the power supply line. shield f ast switching signals like clocks with digital grounds to avoid radiating noise to other sections of the board, and never run clock signals near the analog inputs. avoid cros s over of digital and analog signals. run t races on opposite sides of the board at right angles to each other. this reduce s the e f fects of feedthrough throu gh the board. a microstrip technique is by far the best but is not always possible with a double - sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the so l der side. good decoupling is a lso very important. decouple t he supply with, for instance, a 680 nf 0805 capacitor to gnd. when using the sc70 package in applications where the size of the comp o nents is of concern, a 220 nf 06 03 capacitor, for example, can be used instead. however, in t hat case, the decoupling may not be as effective , resulting in an approximate sinad degradation of 0.3 db. to achieve the best performance from these decoupling components, the user should endeavor to keep the distance between the decoupling capacitor and the v dd and gnd pins to a minimum with short track lengths connecting the respective pins. figure 31 and figure 32 and show the reco m mended positions of the decoupling capa citor for the sc70 and msop packages, respectively. 02930-032 figure 31 . recommended supply decoupling scheme for the sc70 package as can be seen in figure 32 , for the msop package, the decou p ling capacitor has been placed as close as possible to the ic with short track lengths to v dd and gnd pins . the decoupling c a pacitor can also be placed on the underside of the pcb directly underneath the ic, between the v dd and gnd pins attached by vias. this m ethod is not recommended on pcbs above a sta n dard 1.6 mm thickness. the best performance is realized with the decoupling capacitor on the top of the pcb next to the ic. similarly, for the sc70 package, locate the decoupling capacitor as close as possible t o the v dd and the gnd p ins. because of its pinout, that is , v dd being next to gnd, the decoupling capac i tor can be placed extremely close to the ic . the de coupling capacitor can be placed on the underside of the pcb directly under the v dd and gnd pins, but the best perfor m ance is achieved with the decoupling capacitor on the same side as the ic. 02930-031 figure 32 . recommended supply decoupling scheme for the ad7476a/ad7477a/ad7478a msop package evaluating the ad747 6a/ad7477a perfor m ance the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the pc via the eval - board co n troller. the eval - board controller can be used in conjunction with the ad7476acb/ad 7477acb evaluation board, as well as many other analog devices evaluation boards ending in the cb designator, to demo n strate/evaluate the ac and dc performance of the ad7476a/ad7477a. the software a l lows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the ad7476a/ad7477a. see the evaluation board application note for more information.
ad7476a/ad7477a/ad7478a rev. f | page 26 of 28 outline dimensions 1 . 3 0 b s c compliant to jedec standards mo-203-ab 1 . 0 0 0 . 9 0 0 . 7 0 0 . 4 6 0 . 3 6 0 . 2 6 2 . 2 0 2 . 0 0 1 . 8 0 2 . 4 0 2 . 1 0 1 . 8 0 1 . 3 5 1 . 2 5 1 . 1 5 072809-a 0 . 1 0 m a x 1 . 1 0 0 . 8 0 0 . 4 0 0 . 1 0 0 . 2 2 0 . 0 8 3 1 2 4 6 5 0 . 6 5 b s c coplanarity 0.10 sea ting plane 0 . 3 0 0 . 1 5 figure 33 . 6 - lead thin shrink small outline transistor package [sc70] (ks - 6) dimensions shown in millimeters comp liant to jedec standa rds mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0. 25 1.10 max 3.20 3.00 2.80 coplanar ity 0.10 0. 23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-0 7-20 09-b figure 34 . 8 - lead mini small outline package [mso p ] (rm - 8) dimensions shown in millimeters ordering guide model 1 , 2 , 3 , 4 temperature range linearity error (lsb) 5 package description package option 6 b randing ad7476aaksz - 500rl7 C 40c to +85c 0.75 typ ical 6- lead sc70 ks -6 c3v ad7476aaksz - reel C 40c to +85c 0.75 typ ical 6- lead sc70 ks -6 c3v ad7476aaksz - reel7 C 40c to +85c 0.75 typ ical 6- lead sc70 ks -6 c3v ad7476abksz - 500rl7 C 40c to +85c 1.5 maximum 6- lead sc70 ks -6 c3w ad7476abksz - reel C 40c to +85c 1.5 maximum 6- lead sc70 ks -6 c3w ad7476abksz - reel7 C 40c to +85c 1.5 maximum 6- lead sc70 ks -6 c3w ad7476abrm C 40c to +85c 1.5 maximum 8- lead msop rm -8 cey ad74 76abrm - reel C 40c to +85c 1.5 maximum 8- lead msop rm -8 cey ad7476abrm - reel7 C 40c to +85c 1.5 maximum 8- lead msop rm -8 cey ad7476abrmz C 40c to +85c 1.5 maximum 8- lead msop rm -8 c3w ad7476abrmz - ree l C 40c to +85c 1.5 maximum 8- lead msop rm -8 c3w ad7476abrmz - reel7 C 40c to +85c 1.5 maximum 8- lead msop rm -8 c3w ad7476awyrmz C 40c to + 12 5c 1.5 maximum 8- lead msop rm -8 c45 ad7476awyrmz - rl7 C 40c to + 12 5c 1.5 maximum 8- lead msop rm -8 c45 ad7476ayksz - 500rl7 C 40c to +125c 1.5 maximum 6- lead sc70 ks -6 c45 ad7476ayksz - reel7 C 40c to +125c 1.5 maximum 6- lead sc70 ks -6 c45 ad7476ayrmz C 40c to +125c 1.5 maximum 8- lead msop rm -8 c45 ad7476ayrmz - reel7 C 40c to +125c 1.5 maximum 8- lead msop rm -8 c45 ad7477aaksz - 500rl7 C 40c to +85c 0.5 maximum 6- lead sc70 ks -6 c3x ad7477aaksz - reel C 40c to +85c 0.5 maximum 6- lead sc70 ks -6 c3x ad7477aarm - reel C 40c to +85c 0.5 maximum 8- lead msop rm -8 cfz ad7477aarmz C 40c to +85c 0.5 maximum 8- lead msop rm -8 c3x ad7477aarmz - reel C 40c to +85c 0.5 maximum 8- lead msop rm -8 c3x ad7477aarmz - reel7 C 40c to +85c 0.5 maximum 8- lead msop rm -8 c3x ad7477a w armz C 40c to +85c 0.5 maximum 8- lead msop rm -8 c3x ad7477a w armz -rl C 40c to +85c 0.5 maximum 8- lead msop rm -8 c3x ad7478aaksz - 500rl7 C 40c to +85c 0.3 maximum 6- lead sc70 ks -6 c48 ad7478aaksz - reel C 40c to +85c 0.3 maximum 6- lead sc70 ks -6 c48 ad7478aaksz - reel7 C 40c to +85c 0.3 maximum 6- lead sc70 ks -6 c48 ad7478aarm C 40c to +85c 0.3 maximum 8- lead msop rm -8 cjz ad7478aarmz C 40c to +85c 0.3 maximum 8- lead msop rm -8 c48
ad7476a/ad7477a/ad7478a rev. f | page 27 of 28 model 1 , 2 , 3 , 4 temperature range linearity error (lsb) 5 package description package option 6 b randing ad7478aarmz - reel C 40c to +85c 0.3 maximum 8- lead msop rm -8 c48 ad7478aarmz - reel7 C 40c to +85c 0.3 maximum 8-le ad msop rm -8 c48 ad7478 awarmz C 40c to + 8 5c 0.3 maximum 8- lead msop rm -8 c48 ad7478 awarmz -rl C 40c to + 8 5c 0.3 maximum 8- lead msop rm -8 c48 eval - ad7476acb z evaluation board eval - control brd2 evaluation control 1 z = rohs compliant part. 2 w = qualified for automotive applicati ons. 3 eval - ad7476acb z can be used as a standalone evaluation board or in conjunction with the eval - control board for evaluation/demonstration purposes. 4 eval - control brd2 is a complete unit, allowing a pc to control and communicate with all analog device s evaluation boards ending in the cb designator. to order a complete evaluation kit, you will need to order the particular adc evaluation board, for example, eval - ad7476acb, the eval - controlbrd2, and a 12 v ac transformer. see relevant evaluation board app lication note for more information. 5 linearity error here refers to integral nonlinearity. 6 ks = sc70; rm = msop. automotive products the ad7476awyrmz, ad7476awyrmz - rl7, ad7477awarmz, ad7477awarmz - rl, ad7478awarmz , and ad7478awarmz - rl models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automoti ve models may have specifications that differ from the commercial models; therefore, designers should review the specifications section of this data sheet carefully. only the automotive grade products shown are available for use in automotive applications. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models.
ad7476a/ad7477a/ad7478a rev. f | page 28 of 28 notes ? 2002 C 2011 analog device s, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02930 - 0- 1/11(f)

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